Digital parallel correlators have a wide variety of uses in the fields of telecommunications and signal processing.
One application of a digital parallel correlator arises in connection with the spread spectrum communication technique. Spread spectrum techniques permit data signals to be extracted from noise with a relatively small error rate. In a spread spectrum system, a binary 1 data bit is represented by a first sequence of binary states or elements called chips and a binary 0 data bit is represented by a second sequence of binary chips. Typically, the second sequence is the complement of the first sequence. Each sequence of binary chips is known as a spreading sequence.
Thus, in the spread spectrum coding technique, the basic unit of data, i.e., the data bit, is encoded by forming a sequence of chips. The chip rate is much higher than the data rate and each chip has a much broader frequency spectrum than a data bit.
At a receiver, a stream of data bits, which has been transmitted using the spread spectrum format, is recovered using a process known as despreading. Despreading involves the use of a correlator circuit for correlating the received signal which comprises chips with a local reference chip sequence. More particularly, the received chips are entered into a shift register and for each chip time period, the received chips are shifted one position in the shift register. At each chip time period, the number of matches between the local reference sequence and the received chips in the shift register is obtained.
Consider the case where at a despreader the reference sequence corresponds to a binary 1 data bit and the complement of the reference sequence corresponds to a binary 0 data bit. In this case, when the number of matches exceeds a predetermined upper threshold, a data detection decision is made indicating the presence of a binary 1 data bit. When the number of matches falls below a predetermined lower threshold, a data detection decision is made indicating the presence of a binary 0 data bit. In between the data decision times, when there are portions of two connective spreading sequences in the shift register (i.e. the end portion of one sequence and the beginning of the next sequence), the number of matches desirably falls in between the high and low thresholds, thus preventing erroneous data decisions.
In a noise free system, the presence of a binary 1 will be indicated at a data decision time by a total match between the received chips in the shift register and the reference sequence. Similarly, the presence of a binary 0 will be indicated at a data decision time by no matches between the received chips in the shift register and the reference sequence. However, in real systems, noise prevents all the chips in a spreading sequence from being correctly received so that binary 1 and binary 0 data decisions are based on whether the number of matches is above or below upper and lower predetermined thresholds, respectively. This process has the effect of averaging out random noise so that the despread signal component is enhanced and the noise component is reduced.
In short, in a spread spectrum communications system, at an encoder or spreader, each data bit in a data bit stream is coded by transmitting a sequence of binary chips. Typically, one such spreading sequence is used to code binary 1 data bits and its complement is used to code binary 0 data bits. The chips representing the data bit stream are modulated onto a carrier using a conventional two-level modulation technique such as a binary phase shifting keying (BPSK) or frequency shift keying (FSK) and transmitted to a decoder or despreader which includes a correlator as described below. At the despreader, the chips are demodulated and correlated with a reference sequence to reconstruct the original data bit stream in the manner described above.
A digital implementation of a correlator, for use, for example, in a spread spectrum system, comprises a shift register for receiving the transmitted chips and a network for calculating the correlation (i.e. number of matches) at every clock interval, based on a comparison between the chips currently in the shift register and a reference sequence. One type of prior art digital correlator is a parallel correlator available from TRW and bearing the model number TMC 2220 or TMC 2221. This correlator determines the number of matches at each clock interval between the chips in the register and the reference sequence. External circuitry may then be utilized to determine if the number of matches is above or below fixed high and low thresholds.
In a spread spectrum system, wherein each bit is encoded by a certain chip sequence or its complement, the last chips of the old bit are still in the shift register and influence the correlation of the first incoming chips of the new bit. The partial correlation values (i.e. the number of matches) during the transitions between bits (e.g. at the transition between a binary 1 and binary 0) force the fixed high and low detection thresholds to be placed close to the peak correlation values. The peak correlation values occur when there is a complete match or complete mismatch between the chips in the shift register and the reference sequence. The placement of the high and low thresholds near the peak correlation values presents a significant problem. The reason is that when the high and low thresholds are near the peak correlation values, the number of chips received in error that can be tolerated is quite limited.
To mitigate this problem in a conventional spread spectrum system, the spreading sequences used to encode the data bits are chosen so that they exhibit partial correlation values which are as far from the peak correlation values as possible. However, in this case noise-induced errors in the received chip stream tend to shift the partial correlation values towards the peak correlation values and thus towards the thresholds.
Several alternative solutions to the problem of partial correlations at the bit transitions have also been proposed, including for example, the use of peak detection instead of high and low thresholds, the use of adaptive thresholds, or the use of serial correlation rather than parallel correlation. Serial correlation requires synchronization between received and generated sequences and hence requires longer preambles to accomplish synchronization, especially for longer sequences. Peak detection also requires timing information. In contrast, in the case of parallel correlation with fixed high and low thresholds, timing information is straightforwardly derived from the threshold crossings.
In view of the foregoing it is an object of the present invention to provide a parallel correlator with fixed high and low thresholds in which the partial correlations are located as far as possible from the peak correlation values so that the fixed thresholds can be placed as far as possible from the peak correlation values.
It is a further object of the invention to provide a parallel correlator with fixed high and low thresholds in which the effect of noise-induced errors in the incoming chip stream on the partial correlations is minimized.